Contents

Introduction

adms is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile C code for the API of spice simulators. Based on transformations specified in XML language, ADMS transforms Verilog-AMS code into other target languages.

Typical run:

admsXml <vafile> -e <controlfile1>.xml -e <controlfile2>.xml -e ...

Example:

admsXml mysource.va -e myxml.xml

• admsXml reads control file myxml.xml and veriloga file mysource.va. File mysource.html is created.
• Note: files .adms.implicit.xml and .mysource.va.adms are created in background.

The internal data structure of adms is auto-generated from file adms.xml. This file is very important. The rules used to build a control file are based on its contents. More in section Documentations.

Related Links:

• http://sourceforge.net/projects/mot-adms
• http://www.noovela.com

Limitations

• Subset of Verilog-AMS supported

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