Example of translation Verilog-A transistor model MOS1 into ZSPICE

Abstract

This project has been done at the Bauman State Technical University (Moscow). The goal was to:
- learn how to use ADMS and ZSPICE
- learn how to add new models to ZSPICE using ADMS (I implemented MOS level 1 transistor)
- learn how to write ZSPICE netlists
- learn how to run simple zspice tests using the MOS level 1 transistor implemented into ZSPICE

Contents

• MOS1 verilog-ams code
• Full code version
• Verification
• Plots
• Links to related projects

`include "discipline.h"

`define N_TYPE -1
`define P_TYPE +1
`define PI 3.14159265358979323846
...
`define SILICON_PERMITTIVITY 1.0359431e-10

`ifdef insideADMS
`define P(p) (*p*)
`else
`define P(p)
`endif

module MOS1 ( Drain, Gate, Source, Bulk );
inout Drain, Gate, Source, Bulk;

electrical Drain `P(spice:name="d"), Gate `P(spice:name="g"), Source `P(spice:name="s"), Bulk `P(spice:name="b");
electrical IntDrain, IntSource;

parameter integer GENDER = `N_TYPE;

parameter real L = 3.0e-6 `P(spice:name="l" info="Default channel length" type="instance" unit="m");
parameter real W = 3.0e-6 `P(spice:name="w" info="Default channel width" type="instance" unit="m");
...
parameter real VTOTEMPCOEF = 0 `P(spice:name="vtotempcoef" info="Threshold voltage temperature coefficient" type="instance");

integer Reversed;
real Vd, Vs, Vb, Vds, Vgs, Vbs, Vbd;
real Vt, Von, Vth, Vdsat, Vgst, Vc, Vfb, Vto;
real Iss, Idd, Ibs, Ibd, Irs, Ird, Ibulk, Ioffset, Id;
...
real Vexpl, Gexpl;

real Ids 'P(ask="yes");

analog
begin

`ifdef insideADMS
@(initial_model)
`endif
begin
...
end

`ifdef insideADMS
@(initial_instance)
`endif
begin
...
end

...

/* Thershold voltage */

Vth = Vto + Gamma * ( T1s - sqrtPhi );
Vgst = Vgs - Vth;
Vdsat = Vgst;

/* Drain current */

if( Vgst > 0 )
if ( Vgst >= Vds )
begin
betta = Kp * Weff / Leff;
Ids = betta * ( Vgst - Vds / 2.0 ) * Vds * ( 1 + Lambda * Vds );
end
else
begin
betta = Kp * Weff / Leff;
Ids = betta * Vgst * Vgst / 2.0 * ( 1 + Lambda * Vds );
end

/* For P_TYPE */
if( GENDER == `P_TYPE )
begin
Vth = -Vth;
Ids = -Ids;
end

if ( RD > 0.0 )
I(Drain, IntDrain) <+ V(Drain, IntDrain)/RD;
else
I(Drain, IntDrain) <+ V(Drain, IntDrain);

if ( RS > 0.0 )
I(Source, IntSource) <+ V(Source, IntSource)/RS;
else
I(Source, IntSource) <+ V(Source, IntSource);

I(IntDrain, IntSource) <+ Ids;

end

endmodule

After implementation of device mos1.va into ZSPICE you'll get mos1.zsp file ( translation order you can see if you type zspice -h ).
Command zspice --load mos1 shows you that model connected to zspice.
For verification you need to create a simple testcase such as:

mode=circuit
name=dc_Vg_Vd
mode=load
file=mos1.zsp
mode=model
name=mymos1
module=mos1
mode=parameter
name=GENDER
value=-1
mode=model
name=vsource
module=vs

mode=instance
name=mos1
modelID=mymos1
mode=topology
mode=node
name=d
location=1
mode=node
name=g
location=2
mode=node
name=s
location=0
mode=node
name=b
location=0

mode=instance
name=vg
modelID=vsource
mode=parameter
name=dc
value=1.0
mode=topology
mode=node
name=p
location=2
mode=node
name=n
location=0

mode=instance
name=vd
modelID=vsource
mode=parameter
name=dc
value=3
mode=topology
mode=node
name=p
location=1
mode=node
name=n
location=0

mode=dc
mode=sweep
name=vg:dc
start=0.0
end=5.0
step=0.1

mode=save
name=mos1:Ids