| Current view: | top level - src/components/verilog - logic_1.core.cpp (source / functions) | Hit | Total | Coverage | ||
| Test: | qucs-core-0.0.19 Code Coverage | Lines: | 0 | 159 | 0.0 % | |
| Date: | 2015-01-05 16:01:02 | Functions: | 0 | 28 | 0.0 % | |
| Legend: | Lines: hit not hit | Branches: + taken - not taken # not executed | Branches: | 0 | 134 | 0.0 % | |
|
